Zarlink launch digital clock chip

Zarlink Semiconductor Inc. (Zarlink), T1/E1 or PDH (quasi-synchronous digital hierarchy) network equipment, global market leader in timing devices, today launched a new chip DPLL ZL? 30109, the chips for broadband equipment to provide higher flexibility and UC3525ADW datasheet and carrier-class performance. Zarlink applications for the global network to provide the most complete PDH clock chip, ranging from line card clock generation, multiple output, to the central office equipment located in the clock control applications.

ZL30109 chip is a monolithic silicon device is suitable for high-speed terminals and UC3525ADW price and access network equipment, including the DSLAM (digital subscriber line access multiplexer), VoIP gateways and UC3525ADW suppliers and IP-PBX. As a central clock device, the chip reference clock frequency acceptable variety, including the additional 2 kHz (kilohertz) frame pulse and 19.44 MHz (megahertz) clock, to meet various applications.

ZL30109 chip with Zarlinks T1/E1 DPLL whole series of pin-compatible form, add a Zarlink analog clock multiplier PLL product portfolio. The device set in a variety of outstanding features: such as a flexible reference clock to maintain the ability to monitor and excellent jitter performance is better than 0.5 ns (nanoseconds), can easily meet Stratum 4/4E requirements, while providing 19.44MHz SONET / SDH frequency.

ZL30109 and ZL30100 released earlier this year and the ZL30101 DPLL to keep feet on the pin-compatible devices. The new chip can produce a very stable and reliable clock, allowing designers to use the same circuit board design from Stratum 4/4E quickly migrate to the Stratum 3 clock. All features and modes can be selected by the hardware, reduce the need for complex software drivers or an external microprocessor demand.

ZL30109 acceptable two reference clock inputs can be automatically synchronized to any work in the 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz clock frequency. The device is Zarlinks unique processing technology suppress jitter input clock jitter, and can output the following clock frequency: 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz, 32.768 MHz, 65.536 MHz and 19.44 MHz.

As end products and access devices, basic clock control device, ZL30109 chip must ensure that for the duration of network outages or upgrade work. Zarlinks DPLL input reference clock continuous monitoring and detection of the reference clock fails or is lost, the continuous reference clock switching. DPLL in the network or internal system jitter and wander between the case of a stable and reliable output clock.

If the network synchronization clock source is temporarily lost, ZL30109 device will automatically switch to hold mode from past reference signals based on data collected to produce the output clock. System for Stratum 4/4E 0.15 ppm (parts per million) to maintain the extraordinary performance. Zarlink DPLL meet Telcordia GR-1244-CORE for Stratum 3/4/4E, ITU-T G.823, G.824 and G.813 option 1, and ANSI (American National Standards Institute) T1.403 requirements.

ZL30109 DPLL chip production now, with 10 x 10 mm (millimeters) 64-pin TQFP (thin quad flat pack) package. ZL30109 chip one thousand quantities is priced at $ 13.50.