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Electronic information

Actel ARM7 family processor for the FPGA using the development to provide design flow

In Electronic Infomation Category: R | on December   1, 2010

Actels Libero IDE also supports industry-leading static timing analysis and TC7SH04FU datasheet and I / O functions

Actel Corporation announced that its Libero Integrated Design Environment (IDE) adds important new features. The new Libero 6.3 software provides a secure design flow - from synthesis to implementation - in order to Actels CoreMP7 (the industrys first soft ARM7 family processor) integrated into Actels single-chip non-volatile field programmable gate array (FPGA) in the. With this software release, Actel with its industry-leading SmartTime static timing analysis environment, based on minimum delay to provide enhanced support and TC7SH04FU price and a unique way to achieve high-speed FPGA-accurate time keeping features. The enhanced software also automates I / O voltage assignments, and TC7SH04FU suppliers and support for Actels new RTAX4000S device - the industrys highest density of space applications in the FPGA.

Actel tools market, said Michael Mertz, senior manager: "Libero 6.3 IDE with the industrys best third-party EDA tools, and Actels proprietary design tools, Actel continues to provide unmatched multi-function tool kit value of tradition. By Tisheng Libero to support the implementation of soft ARM7 family processor, we enable FPGA designers to enjoy the Zhezhong more advanced microprocessor technology. Moreover, the previous manual operation through automation, and provide a unique timing analysis, FPGA designers can quickly get the best results. "

Optimized to support CoreMP7

Libero 6.3 provides an advanced block-level way for designers to gather around the CoreMP7 IP, and to predictable timing and verify operation, its mapping in Actels ProASIC3 / E FPGA structure. Libero 6.3 is tightly integrated from Magma Design Automation, Mentor Graphics and Synplicitys industry-leading third-party tools, so CoreMP7 is designed to be integrated seamlessly integrated, verification and physical synthesis. Synplicity and Magma Design Automation of the synthesis and physical synthesis tools have advanced black-box support, the design process to achieve security, while Actels proprietary tools provide modern encryption technology to protect the valuable ARM7 IP from illegal access. Actels tools also provide the necessary timing analysis and layout features to simplify and accelerate system design using CoreMP7.


and SRAM-based devices different, Actel Flash difficult invasive architecture and powerful encryption technology ARM7 and user protection against reverse engineering or theft of IP issues affecting, to help protect the companys competitive advantage and development investment. Actel Libero 6.3 devices to provide a unique end to end security process, allowing the first to ARM processor-based technology in programmable logic as a soft IP core implementation. Results, the designer for a variety of value-based consumer electronics, industrial, automotive and high-reliability applications, the cost of building unique solutions for the economy.


Advanced features and new device support

Libero 6.3 delivers enhanced timing and layout capabilities, to promote better design implementation and improve designer productivity. Actels industry-leading SmartTime timing analysis environment now has a "strengthening of the minimum delay" (Enhanced_Min_Delay, EMD) function, the first time this comprehensive process to maintain accurate time analysis of the introduction of the FPGA design. EMD eliminates the need for minimum delay can be overly conservative operation, to improve the system design timing closure. This remarkable performance in a unique way to bring advantages to SmartTime users, through a more comprehensive method to verify the internal and chip-to chip-level setup and hold timing.

Libero 6.3 also features an advanced matching algorithms to automate I / O voltage distribution, ease complex processor-based design of time-consuming process, to optimize I / O configuration. This new I / O library distributor in the layout process can automatically VCCI voltages and VREF pin assignment has not been assigned to the appropriate I / O in. Will be done this previously manual process automation to simplify the FPGA design, especially contain up to 80 different types of I / O complexity of the device.

Addition, Libero 6.3 provides the tools necessary for new RTAX4000S Actel devices using a new generation of high-reliability design space calibration, layout and verification operations. RTAX4000S with four million system gates, is the industrys highest density radiation-tolerant FPGA.

On the Libero Integrated Design Environment

Actels Libero 6.3 IDE integrates the most prominent partners from the EDA advanced design tools, including Magma, Mentor Graphics, SynaptiCAD, and Synplicity, and other major EDA companies, and custom development by the Actel tools, integrated into a single FPGA development kit in. Libero tool suite supports mixed-mode design entry, so that designers can choose the design will be advanced VHDL or Verilog HDL language modules mixed with schematic modules.

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