Cadence Guo-Jun Liu: China has gradually have the 65nm chip design capability

Few years ago, 65nm chip design projects have been launched in China one after another up. China has been gradually chip design companies have the 65nm chip design capabilities. Meanwhile, the 65nm feature size and DSP56001AFC27 datasheet and ever more There is a big design projects, so that, on some important aspects to the upstream and DSP56001AFC27 price and downstream industries of common concern.

A concern to ensure IP quality IP issues and DSP56001AFC27 suppliers and

Although not directly related to 65nm chip design, as some of their customers in the actual design of the project encountered problems is one of the larger IP quality issues, and should therefore lead to the industrys attention.

With a more advanced chip design technology, the chip size increases, more and more demands on the IP.

Present different IP sources, different foundries, how to integrate and verify the IP, in particular the quality of verification IP has become a large-scale SoC design, an increasingly important issue. If the IP did not meet the performance, as described on the SPEC will affect the performance of the entire SoC, resulting in customers must re-designed to bring great loss to the customer. In this case, the industry need to focus on resolving several issues: First, how to verify the specified foundry IP, understand its reliability. The second is how to understand the quality of IP.

This end, Cadence start the Cadence Open IntegratiON Plat-form platform concept. The platform includes the IP validation and quality certification and other technical means and, more importantly, through the platform, Cadence group of experienced technical staff can be good for the application of IP, how to integrate IP, IP quality testing and other related issues for clients to provide advice. At the same time, Cadence will also provide IP design related services. Unlike selling general merchandise to sell as IP, IP Be sure to include relevant environmental and capacity, especially in technical support and services. The Cadence is just a more comprehensive approach to resolve issues related with IP.

Concerned how the hardware and software co-verification II

With the increase of chip scale, chip design verification work has occupied the leading position. Some industry statistics indicate that the current chip, chip design verification has occupied 70% of the workload. At the same time, the SoC or complex process of chip design, software design work much faster growth rate than hardware, therefore, the chip has been verified not only the traditional sense of design-related hardware logic simulation and timing verification, but hardware and software co-verification.

Cadence is the invention of the chip verification tool company. With the trend of hardware and software co-verification, Cadence also provides a hardware emulator, hardware and software co-verification platform and the software simulator together to achieve complex SoC verification methods. Cadence Incisive PallADIum and Xtreme Ⅲ system-level verification platform, the process of verification in hardware, allowing the chip companies also do software development, to accelerate system development speed. If 5 years ago, some design companies can also use artificial means or to buy more stations to carry out verification of chip design, to today, the chip design complexity so that they have no way to avoid the. Last year, the CAS Institute of Computing on the use of the Cadence Incisive Xtreme Ⅲ system, accelerated more than 64 million of its next generation, "Godson-3," Advanced multi-core processor RTL design and verification flow development.

Focus on three C language step by step practical chip design

Until today, chip design has been using hardware description language, but the low-level language and C language and other high-level language compared to simulation speed is slow. To this end, the chip design industry has long made demands on the C language, various EDA tools 10 years ago, companies started to develop related technologies. Cadence is also high-level language was designed to make the concept of the chip, but until a few years ago not to go practical. However, the C language to the last two years has made great progress in chip design, EDA tools for business-to-C language to RTL optimization work has been done quite well, able to achieve human level. Cadences C-to-Silicon Compiler in Japan, some companies have begun to use. Moreover, the latest news, Casio uses CadenceC-to-Silicon Compiler design for high-level synthesis has been completed, allowing the industry to see the chip design using C language of hope. If the C language to design chips, but also make hardware and software co-design and verification becomes convenient.

The past few years, C language design chips may be gradually moving towards reality. To this end, Cadence has already begun in China, gradually extended C-to-Silicon related technologies. However, different from general software design, application of C-to-Silicon design engineers need to have the C language and dual chip design experience, which the engineers also made new demands.

Concerned about low-power design from RTL four-start

Known as leakage current, 65nm and below chip design to solve the key problems is power consumption. In the low-power design, the real low-power design should start from the RTL, this is very critical. Optimization started from the front to the back end began to effect optimization is very different. If the wait time to consider chip power optimization problem, then the degree can reduce power consumption is very limited. From the front-end design to begin to consider power optimization, then to the back end, this effect will be multiplied apparent. Under this concept, Cadence set up a complete low-power design flow, in each link to provide low-power design methods and tools. The Cadence low-power verification flow, and other links in the logic and implementation must take into account power consumption. The design process is currently in the design of mobile devices, the success of the chip.

Concerned about the number five mixed design should be unified database

Chip design for discrete devices experienced a first full-custom design of small, small-scale and large-scale digital design, digital design stages. There was a time, digital design is the industrys concerns, but now make SoC design mixed digital-analog design becomes increasingly important.

Mixed-design one of the trends is to a large-scale digital circuit design and analog circuit design conducted in the same database and the database to cover the front and back. And Cadence has the Virtu-oso full custom digital and analog mixed Encounter design platform and a large-scale digital circuit design platform together, using a single database, so that large-scale analog circuits and digital circuits can achieve interactive design. The unified database called OpenAccess, Cadence it open to the industry. Concerned about the six-chip design process

to consider DFM

The 65nm chip design before the design for manufacturing (DFM) and design enterprises do not need to be considered, it was fab issues to consider; in 65nm, the chip design companies also have to consider the design for manufacturing. This is an important trend. Design for manufacturing, including chip companies need to build more libraries, such as memory, high-speed I / O and so on. Currently there are a lot of customers, particularly to do high-performance products to customers, to help them find Cadence low-power library building, which is a clear trend.

Although Cadence has the hardware and software co-verification, low power, mixed-signal the consolidated database, DFM, C-to-Silicon and achieved some results, but there are a lot of things to do. Currently, the application-driven system-level design, OpenIntegrationPlatform (IP Integration Platform), the development of more advanced technology nodes continue to put our focus.