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View: 3D technology, the electronics industry needs for three major reasons
In Electronic Infomation Category: R | on December 1, 2010
Recently, the 3D advertising everywhere. The first 3D television has begun selling; TV shows are beginning to use 3D technology plays, most of them sporting event; while many films released eye-catching 3D version. However, 3D technology has not only been used in consumer electronics and LM2439T datasheet and entertainment, 3D extraction technology (3Dextraction) was also used in some areas of IC design. Designers attempt to design improved forecasting performance and LM2439T price and other behavior after accuracy. P>Why use 3D extraction technology
? It all comes down to the design and LM2439T suppliers and production needs, from a design point of view, a more accurate simulation of circuit model in the time available to the designers, such as timing, power and noise performance characteristics, as well as other important parameters such as gain, bandwidth and reliability. P>What
lack of extraction technology? P>
Large traditional EDA vendor tools are polarization. On the one hand, 2.5D geometry layout extraction equipment browser, device and interconnect, and pre-characterized to find the matching pattern. When a match is found, when it began to check the size, run some calculations to generate R and C values for the back label (back-annotation) in the network table. In terms of these products, capacitors are usually very few problems, its performance is usually acceptable (although the run time, it is because a series of more complex detection mode); more and more is the accuracy problem. For example, Figure 1 shows a typical MOMCAP structure, which is due to 3D for 3D topological structure needs to ensure the accuracy of the 2D or 2.5DExtractor not accurately deal with this topology. P>
In a more advanced process nodes, designers need to extract a combination of increasingly complex in a heap of metal interconnect stack part, and between the device and the interconnection between the crosstalk between the edge and shielding capacitance distributed RC model. And do not forget the substrate. 2.5D extraction because the lack of accuracy required for nanometer design, designers have had to take a conservative or passive design techniques, the use of sub-optimal design. Otherwise, it is designed to fail. P>
The current lack of 3D extraction technology what? P>
The other hand, the existing 3D extraction technology, to a large EDA company (field solver - using finite element, finite difference, boundary element or a similar method for the Maxwell equations provide accurate solutions program), in the face in the face of todays large and complex design, its low efficiency, in addition to careful use of other than focusing on anything in terms of its running time is unrealistic. Supporters of these tools are often explained that the enlarged grid, running time can be improved, and it does work. But to a considerable loss of accuracy to obtain. In order to obtain the accuracy required for the design of today must have a fine-grained or dense grid, which will exponentially increase the run time and memory footprint. In addition, dense grid, boundary conditions have to compromise with lower memory footprint, to control the use of memory, which reduces the field solver extraction of elements in the surrounding of the "interaction region", ignored or not accurately describes the geometry around a little, and further affect the accuracy. P>
What is needed is a more accurate 3D extraction technology? P>
3D is now needed is access to technology innovation, and to go beyond the limitations of existing solutions. This solution should be provided without the need for complex set of consistent and accurate network table, and to achieve sufficient to support the chip in a wide range of complex, scalable networks and regional boundaries running time. Front in Silicon Valley (SiliconFrontline), we are introducing products 3D field solver, the use of new technologies, so designers can use all the features of advanced process nodes, including the new device types and DFM structure, while reducing the number of repeated checking. P>