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Electronic information

Zarlink Introduces Industrys Lowest Jitter Single-chip synchronizer

In Electronic Infomation Category: R | on December   1, 2010

(Electronic markets Reuters) Zarlink Semiconductor (NYSE / TSX: ZL) today introduced the industrys first for the SONET / SDH multi-service applications, single-chip ultra-low jitter synchronizer. The feature-rich ZL ? 30116 and LT1206CS8 datasheet and ZL30119 PLL (phase locked loop) is the lowest jitter and LT1206CS8 price and smallest for the management of the OC-48/STM-36 rate SONET / SDH Stratum 3 synchronization of the device. With Ethernet and LT1206CS8 suppliers and other packet-based explosive growth of communications, carriers must protect their SONET / SDH infrastructure investment while providing a variety of traffic types. Network equipment vendors are developing SONET / SDH multi-service products, including the MSPP (multiservice provisioning platforms), and MSSP (multiservice switching platforms), allows operators to the edge of the network through the replacement of equipment only to mix voice and packet services. Industry research shows that in 2005 the market capacity of 35 billion U.S. dollars, equipment installation expected in 2006 will grow 26%.
turn, semiconductor companies are delivering next-generation ADM (add-drop multiplexers), which is a small size, high performance SoC devices can be more efficiently handle packet traffic. ADM need to use multiple clocks to handle multiple traffic types, only Zarlinks new clock chip designers for ADM Stratum 3 clock to provide a full range of integrated capabilities, while meeting OC-48/STM-16 performance requirements.
"Our new synchronization platform technologies and digital and analog PLL clock advanced combination of comprehensive capabilities for SONET / SDH multi-service equipment designers the performance they need," Zarlink Semiconductor Product Marketing Manager Michael Rupert said. "ZL30116 and ZL30119 chips offer maximum flexibility and ease of design, while significantly reducing material costs."
Leading network equipment vendors are currently evaluating Zarlinks new PLL for their next generation products for evaluation.
a full set of output clock and synchronization capabilities
AdvancedTCATM highly programmable ZL30116 and ZL30119 chips of results in three separate clock line, eliminating the need for external dividers or clock multiplier PLL. These devices can meet any commercial SONET / SDH PHY (physical interface) of the reference frequency requirements, providing the industrys widest range of optional low-jitter clock output frequency - 19.44 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 311.04 MHz and 622.08 MHz.
ZL30116 device to achieve the markets most comprehensive master / slave clock redundancy. The chip is the only function of the built-zero delay PLL synchronizer, external clock propagation delay through the compensation to meet the strict AdvancedTCA bus clock phase alignment requirements.
single-chip design saves space, management shake

SONET / SDH equipment, digital PLL-based synchronization control in a multi-service switching environment, manage a large clock. However, most digital PLL for rates higher than OC-3 interface will have a greater jitter, and therefore must use a separate analog PLL to "eliminate" noise. Multi-chip module or combination of programs might need one square inch of the layout of the space. Zarlink is the first to provide less than 1 ps jitter single-chip synchronous device manufacturers. ZL30116 Stratum 3 system synchronizer and ZL30119 line card synchronizer pin-compatible, size is only 9 mm x 9 mm.
carrier-class network synchronization
ZL30116 and ZL30119 devices provide superior network synchronization features, including the clock and the reference clock to maintain a seamless switch. These chips can monitor the input reference clock to the reference clock in the detection of weak or failed to provide seamless switching reference clock to ensure that the network interruption or continuous operation during the upgrade. The PLL can be network or internal systems in the presence of jitter and wander between the case of the state to maintain stable and reliable output clock.
If the network synchronization clock source is temporarily lost, the device will automatically switch to hold mode, and the past data collected from the reference signal to generate output clocks.
Availability
ZL30116 and ZL30119 PLL is available now.

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