ADI Introduces Industrys best performance of the 6 channel and 12-channel compact clock buffer

Analog Devices, Inc., Has recently introduced the industrys best performance of the 6 channel and TCA785P datasheet and 12-channel clock buffers compact, low-jitter performance is suitable for applications that require high-speed applications. Competitive compared with similar devices, ADIs 12-channel ADCLK954 LVPECL and TCA785P price and ADCLK854 LVDS / CMOS, and TCA785P suppliers and 6-channel ADCLK946 LVPECL and ADCLK846 LVDS clock fanout buffer in a single chip to provide four times the clock channel, and a better jitter and skew performance. ADIs LVPECL (low-voltage pseudo emitter-coupled logic) low jitter fanout buffers 75 fs (femtoseconds), LVDS (Low Voltage Differential Signaling) / CMOS low jitter fanout buffers 100 fs. In addition, ADCLK9xx clock buffer with 9ps (ps) and low skew. ADCLK854 clock buffer provides 24 CMOS (complementary metal oxide semiconductor) channel.

With the above performance indicators, these clock buffers are suitable for high-speed ADC (analog / digital converter) and DA (D / A converter) clock, suitable for applications such as wireless infrastructure equipment, medical imaging and industrial applications that require high speed, high channel density and excellent timing performance of high-performance applications.

In addition, 6 to 12 clock channels can reduce the component count and board space while simplifying high-speed signal chain design and reduce the total bill of materials cost.

- Jitter and skew performance breakthroughs; better performance of the converter clock

12-channel ADCLK954 and 6-channel ADCLK946 LVPECL fanout buffers are available in industry-leading jitter and skew performance, allowing design engineers to achieve higher ADC or DAC SNR (signal to noise ratio). 4.8GHz ADCLK954 by IN_SEL control pin provides two selectable differential input. The two inputs with a 100 Omega-chip termination resistors may be differential or single-ended clock source with the work.

- Faster conversion clock; lower power consumption

12 LVDS/24 CMOS channel ADCLK854 and 6 LVDS/12 CMOS channel ADCLK846 100fs jitter can provide high timing performance. All of these clock buffers are available to design engineers benefit from the high-speed ADC and DACs full-resolution and performance, while maintaining the operating frequency of 100MHz 12mW per channel, low power consumption. ADCLK854 offers two optional input and sleep mode function. IN_SEL pin fan-out state to decide which input to output, SLEEP pin enabled sleep mode to turn off the device, the input support a variety of single-ended and differential logic levels, including LVPECL, LVDS, HSTL (high-speed transceiver logic), CML (current mode logic) and CMOS.